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Documentation for process uart.transmitter.structure.baudpr

VHDL contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  --
    3  -- Process 'baudpr' in architecture 'structure' of entity 'transmitter'.
    4  --
    5  --------------------------------------------------------------------------------
    6  --
    7  -- Copy of the interface signals:
    8  --
    9  -- sclk   : in     std_logic;
   10  -- tx_clk : out    std_logic;
   11  -- resetn : in     std_logic;
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  baudpr: process (sclk) is       -- EASE/HDL sens.list
   16  begin
   17    if resetn = '0' then
   18      tx_clk <= '0';
   19      cnt   <= 0;
   20    elsif rising_edge (sclk) then
   21      if cnt = 0 then
   22        tx_clk <= not tx_clk;
   23      end if;
   24      if cnt = 7 then
   25        cnt <= 0;
   26      else
   27        cnt <= cnt + 1;
   28      end if;
   29    end if;
   30  end process baudpr ;
   31