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uart

transmitter

structure

Documentation for process uart.transmitter.structure.edgedet

VHDL contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  --
    3  -- Process 'edgedet' in architecture 'structure' of entity 'transmitter'.
    4  --
    5  --------------------------------------------------------------------------------
    6  --
    7  -- Copy of the interface signals:
    8  --
    9  -- tx_clk    : in     std_logic;
   10  -- neg_txclk : out    std_logic;
   11  -- resetn    : in     std_logic;
   12  -- sclk      : in     std_logic;
   13  -- tx_clk_o  : out    std_logic;
   14  -- tx_clk_o  : in     std_logic;
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  edgedet: process (tx_clk, resetn, sclk) is      -- EASE/HDL sens.list
   19  begin
   20    if resetn = '0' then
   21      neg_txclk <= '0';
   22      tx_clk_o  <= '0';
   23    elsif rising_edge (sclk) then
   24      if tx_clk = '0' and tx_clk_o = '1' then
   25        neg_txclk <= '1';
   26      else
   27        neg_txclk <= '0';
   28      end if;
   29      tx_clk_o <= tx_clk;
   30    end if;
   31  end process edgedet ;
   32