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uart

transmitter

structure

Documentation for process uart.transmitter.structure.reg

VHDL contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  --
    3  -- Process 'reg' in architecture 'structure' of entity 'transmitter'.
    4  --
    5  --------------------------------------------------------------------------------
    6  --
    7  -- Copy of the interface signals:
    8  --
    9  -- resetn : in     std_logic;
   10  -- addr   : in     std_logic_vector(1 downto 0);
   11  -- csn    : in     std_logic;
   12  -- wr     : in     std_logic;
   13  -- data   : in     std_logic_vector(dwidth-1 downto 0);
   14  -- sclk   : in     std_logic;
   15  -- ld     : out    std_logic;
   16  -- d      : out    std_logic_vector(dwidth-1 downto 0);
   17  -- 
   18  -- EASE/HDL end ----------------------------------------------------------------
   19  
   20  reg: process (resetn, sclk) is      -- EASE/HDL sens.list
   21  begin
   22    if resetn = '0' then
   23      d  <= (others => '0');
   24      ld <= '0';       
   25    elsif rising_edge (sclk) then
   26      if csn = '0' and wr = '1' and addr = "00" then
   27        d <= data; 
   28        ld <= '1' after 10 ns, '0' after 20 ns;
   29      else
   30        ld <= '0';
   31      end if;
   32    end if;
   33  end process reg ;
   34