Back

Index

uart

uart

structure

Documentation for concurrent statement uart.uart.structure.oe

VHDL contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  --
    3  -- Concurrent Statement 'oe' in architecture 'structure' of entity 'uart'.
    4  --
    5  --------------------------------------------------------------------------------
    6  --
    7  -- Copy of the interface signals:
    8  --
    9  -- data  : inout  std_logic_vector(dwidth-1 downto 0);
   10  -- rd    : in     std_logic;
   11  -- d_out : in     std_logic_vector(dwidth-1 downto 0);
   12  -- d_in  : out    std_logic_vector(dwidth-1 downto 0);
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  
   17  data <= d_out when rd = '1' else (others => 'Z');
   18  d_in <= data after 5 ns;--, "000000" after 10 ns;
   19