What's new in EASE™ 9.5

Loading older projects

Each time you load a project which has been created with an older version of EASE a message box is activated:

This is to remind you that if you save the project with current EASE it can no longer be open in older versions of EASE. This message box can be disabled in the User preference dialog on the Application page.

Block diagram editor

Concurrent statements ordering

The order in which all concurrent blocks (generates, instances, processes, etc) in a block diagram are shown in the browser and generated in VHDL or Verilog can be explicitly set using the ‘Define order of blocks’ dialog. By default the order is ‘Automatic’, which is the order in which all the blocks have been created.

This dialog can be activated with the ‘Order of blocks in the generated HDL…’ menu item in the diagram context menu and through the browser architecture context menu.

Support for VHDL case-generate and if-elsif-else generate blocks.

The generate statement has been extended to support case generate and if-elsif-else generate statements. The VHDL standard needs to be set to VHDL 2008.

Double clicking on a generate block will open the first generate diagram present. You can navigate to the other generate diagrams using the context menu of the generate block, or by doubling clicking on the desired diagram inside the database browser.

If/Else gnerate block browser — If/Else generate block in the database browser

FSM diagram editor

The following shortcuts have been added:
T,L: toggle label visibility for selected objects

The following 1 letter shortcuts where changed in 2 letter shortcuts:

	Add action:	A => A
	Add curved transition:	C => A, C
	Add hierarchical state:	H => A, H
	Add rest state:	R => A, R
	Add state:	S => A, S
	Add straight transition:	T => A, T

VHDL / Verilog changes

Verilog attribute declarations

Verilog attributes can now be defined for ports, wires and instances in the appropriate properties dialog of the object. They are placed in the Verilog code directly in front of the declaration using the ‘(* keep = true *) syntax. If no value is specified for the attribute name only the attribute will be generated between the ‘(*’ and ‘*)’ markers.

Verilog atttributes on a net — Verilog attributes on a net

VHDL Library ‘work’

Do not generate references to library 'work' inside context declarations (VHDL-2008 LRM 13.3).

Batch mode HDL import

Added some special options to the ease_cmd executable to import HDL files using the command line executable:

ease_cmd -import -sv [2005|2009|2012|2017] <import project> <import file>
ease_cmd -import -verilog [95|2001|2005] <import project> <import file>
ease_cmd -import -vhdl [87|93|2008] <import project> <import file>
	<import project>: Ease.ews directory (may or may not exist)
	<import file>: each line in this file contains either:
		<full path to file>
		<library name>##<full path to file>

These commands cannot be combined with other command line options (like -tcl) to make sure no inconsistent projects are saved.

Importing ‘black box’ units

VHDL entities or Verilog modules from other EASE projects can now be imported as a block box. This allows you to instantiate the unit without requiring the complete hierarchy of this entity/module to be present in the current project. Any package uses required to instantiate the unit need to be added manually.

The import dialog is started from the library context menu in the database view using the ‘Import → Units as black box… menu item.

Linting

The following lint checks for the DO-254 standard have been added:

SS8: Avoid using clock as data.
SS9: Avoid shared clock and reset signal.
SS10: Avoid gated clocks.

Other improvements

Id 2241: Option to disable verification message 'Net has only one connection'
Id 2248: When deleting temporary files also delete empty directories inside ease.hdl directory.
Id 2254: Allow import of individual objects (as black box) from other Ease projects.
Id 2269: (System)Verilog import now supports simple unary operators in a port connection.