IO Checker is the best tool to exchange data (and verify consistency) between FPGA design and schematic capture.
HDL Works has developed an Altium Designer extension to form a bride between the schematic capture design and IO Checker. The extension allows you to:
The interface can be used for both initial wiring of components or to update existing schematics because of changes in the pin assignments of the FPGA. For power and ground pins you can add a wire or place a note about the required voltage near the pin. LVDS DIFFPAIR parameters can be added for the LVDS signals and NoDRC attribute to unconnected pins.
Automatically adding wires to components of a large FPGA saves valuable time and guarantees equal signal names in both design environments.
The extension is available for Altium Designer 18 and later. Please contact HDL
Works for instructions on how to download and install the Altium Designer
(We are waiting for Altium to review the extension so it can installed from within Altium Designer)
More information on the IO Checker features and its smart verification methodology can be found on the main page.
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