AMD (Xilinx) FPGAs
IO Checker supports all FPGA families from AMD in both the ISE and Vivado tool suites
Device families include all low power,
automotive and defense grade versions.
ISE generates a pad report file (extension 'pad' (and an equivalent '_pad.csv')) which can be used.
Vivado generates a pin report file (with suffix '_io_placed.rpt') which is processed.
IO Checker both reads and writes the Vivado XDC and ISE USF constraint formats.
- Artix 7
- Artix UltraScale+
- Kintex 7
- Kintex UltraScale
- Kintex UltraScale+
- Versal (AI Core, AI Edge, Prime, Premium)
- Virtex 7
- Virtex UltraScale
- Virtex UltraScale+ (HBM, 58G)
- Zynq UltraScale+ (RFSoC, MPSoC)
- Spartan 3, 3A, 3AN, 3A-DSP, 3E
- Spartan 6
- Spartan 7
- Virtex 4, 4QV
- Virtex 5, 5QV
- Virtex 6
Wiring schematic symbols
Copyright © 2004 - 2023 HDL Works