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Signal View

IO Checker Signal view
IO Checker Signal view

The Signal view is used to assign location constraints and IO standards to signals. The data can be retrieved from the constraints, CSV file(s), a VHDL / Verilog file or imported from the PCB data. The import can suppress LVDS negative signals and different ways to edit groups of signals are available. The view can be used to create locations constraints using drag & drop to the pin- or device view; create a VHDL entity or Verilog module, exported to a CSV file or used to wire FPGA symbols in a schematic.

When ready the view data can be used to create or update constraints for the support FPGA vendors. Keeping your constraint file order and comment un-modified.

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