Symbol tool

The IO Checker symbol tool is designed to create symbols for various PCB design tools in a fast and easy way. The large pin count of FPGAs makes creating symbols in most PCB packages a cumbersome task.

HDL Works decided to develop a symbol tool based on its FPGA database. So it is aware of IO banks, LVDS pairs, control pins and various power pins. The symbol tool is a pin grid position based tool where each pin should be assigned to a symbol, a symbol side and a grid position. From this data a rectangular symbol is generated with the pins located on the specified side and grid position.

Pins can be assigned to a symbol in the pin view, using a wizard, or by various merge and split actions. The (Pre)View window directly shows the results and allows you to adjust pin positions on the symbol.

Non visual attributes can be specified in the project properties and will be applied to the appropriate objects in the selected schematic capture tool.

Wizard

A wizard allows you to create initial symbols in seconds. In IO Checker all FPGA pins are assigned to a category. Together with the bank information and known LVDS pairs pins can be assigned to a symbol. Next, the user preference determine the amount of pins on a symbol and how user IO pins are distributed on the symbol sides.

FPGA pin labels can be adjusted using regular expressions to remove characters not allowed in your schematic capture tool or to truncate long labels.

Symbol (pre)view

The Symbol (pre)view is both a preview window for the symbols and an editor for pin and label placement locally on a symbol. Changes in the pin table are directly visible in the preview.

Pins and labels can be selected and moved to another position. When a pin position is occupied just wait a second and the pins will be pushed either down or to the right. Pins can be moved beyond the bottom (left and right placed) or right (top and bottom placed) and the symbol size is adjusted automatically.

Labels have a default position but can be moved anywhere you like.

Moving pins around

Schematic capture tools

The only schematic tool dependent data are the pin types. Each tool uses its own set of pin type names. The symbol tool translates the IO Checker database information to the appropriate pin type when importing a device.

The final symbol generation is done through a Tcl interface. This allows for customer tuning of the symbols and makes it easier to add new formats. The first release of the Symbol tool supports Altium Designer, Cadence Allegro & System Capture, Kicad and Pulsonix.
New schematic capture formats can be added on request.