The Pin view shows the information extracted from the FPGA pinlist, constraint file(s) and PCB netlist. It shows pad name, bank number, the FPGA signal name, IO Type, PCB signal name and when available the constraint signal name and I/O type for each pin. In front of the PCB signal an icon is showing with recognized type of the PCB net when appropriate. It shows also voltage errors and warnings.
You can organize the Pin view using various sort options and filters so you can concentrate on the potential mismatches. Each columns has its own dedicated tooltip for additional information.
The PCB netlist parsers extract the power and ground nets for the FPGA and recognize pull-up, pull-down, decoupling, dangling and un-connected circuits. When a pull-up or decoupling circuit is recognized the connected voltage is added to the PCB signal name.
The view can be sorted in various ways (like by severity (errors), by pin name, by fpga signal name, by pcb signal name). Both column and rows can be hidden using filters.
The Signal view is used to assign location constraints and IO standards to signals. The data can be retrieved from the constraints, a CSV file, a VHDL / Verilog file or the PCB data. Signal names can be edited to fix identifiers issues present when imported PCB data. The view can be used to create locations constraints using drag∧ drop to the pin- or device view; create a VHDL entity or Verilog module, exported to a CSV file or used to wire FPGA symbols in a schematic. You can filter already assigned signals to concentrate on the unassigned signals only.
Copyright © 2004 - 2022 HDL Works