What's new in IO Checker™ 4.1

Netlist readers

Support for the following netlist formats has been added to IO Checker:

The project properties dialog shows an additional PCB option page when the PCB format is Cadence Allegro board or packaged netlist file(s) on which you can disable the voltage extraction. The generic EDIF and VeriBest EDIF netlist parsers have been deprecated.

Sorting of the pin view

The pin view can now be sorted by clicking in the header section. A small down-arrow will indicate which row is used. The header label you select will be used as primary sort column. If you select a new header label as primary sort column, the previous one will become the secondary sort column.

Pinview header sorting
Pinview header sorting

PCB ground net

It is now possible to explicitly set a net to be a GROUND net when it is connected to an FPGA pin which is in the GND group using the context menu item ‘Set/unset PCB net as a ground net...’ of the pin view.

Netlist determination

The recognition of voltages has become more strict to prevent a negative voltage to be recognized as positive. It can imply that when you re-process the PCB netlist of a project which didn’t have any voltage errors, it no longer recognizes the voltages. When this is the case you can either specify them manually or add corporate power rules to determin the voltage. Please contact us if would like help on defining corporate power rules.

Xilinx constraint file processing

In Xilinx, IO constraints can be set for an array using the signal name (without indication it is an array, like ‘{signals}’ while IO Checker required ‘{signals[*]}’). IO Checker will now change the implicit wildcard to an explicit wildcard, but only if it is able to determine that it is dealing with an array. This means it will only work if there were previous constraints (e.g. location constraints) for one of the elements.

Wiring a Cadence Allegro symbol based on a CSV file

The dialog to wire non-FPGA symbols in Cadence Allegro has been extended with a ‘Column of the ref. designator’ entry. When it is set the function can wire multiple symbols in a Cadence Allegro schematic.

User and corporate location dialog

IO Checker can use a number of configuration files, which can reside in the user or corporate location. To simplify the use of these configuration files and show which files are present a new ‘User and corporate configuration files dialog’ is used. The dialog allows you to setup (create/edit/delete) configuration files for which no user interface is present. New files are created using a template from the installation showing you the required format.

User and corporate dialog
User and corporate dialog

Altium Designer extension

IO Checker has been extended with a simple TCP/IP communication interface to exchange data between Altium Designer and IO Checker. When you start IO Checker from the extension a message is printed to the log window about the TCP/IP port used. When wiring FPGA symbols or exporting a netlist to IO Checker the extension will use the channel to retrieve information from the selected IO Checker project.

A new ‘Task’ has been added to just generate an XML netlist file to be able to use this netlist on another computer. The XML netlist file generated by the extension is located in the ‘_hdlworks’ folder of the AD project and is named <AD_project>.xml

Device Support

The following device families (or additional devices) have been added:

Download IO Checker 4.1 now:


Home dot Company dot Products dot Sales dot Support dot HDL Corner dot Site Map
Copyright © 2004 - 2020 HDL Works