What's new in IO Checker™ 5.0

Improved high resolution monitor support

Buttons with images and other graphical user interface elements will follow the scale size set in Windows and Linux.

In the User preference dialog, Application page, you can specify a font size increase, which will increase all font sizes for application text, for which you cannot select the font and size in the preference options (like in menus, dialogs and tab labels).

Pin view

The context menu of the pin view has been simplified. The ‘Accept name mismatch’ and ‘Accept power mismatch’ entries have been merged in ‘Accept mismatch’. The item 'Change accept comment' has been added to change comment on a user accepted mismatch.

The items ‘Set/unset PCB net as a ground net…’, ‘Specify PCB voltage…’ and ‘Clear PCB voltage’ are moved in to the sub-menu ‘PCB net type’. Automatic is the default and should be used to remove the ground net of PCB voltage setting. Use ‘Other’ to force a net which was recognized as either ground or power net to be a regular user IO net.

The netlist type of a net can be set on any net. In the past power a voltage value could only be set on a net connected to a FPGA power pin. If a PCB net is manually marked as being a ground net we will now show this in the pin view by adding ' (-> GND)' to the name.

Device view

The device view now shows pin labels for QFP packages.

Pins which are reserved, but different than do-not-use (like RSVDGND from Xilinx) show an R symbol.

Pins which can be both configuration and user IO have a diamond symbol inside the boundary.

Matching & verification

The following changes have been made in the FPGA - PCB verification:

The ‘Accept power mismatch’ and ‘Accept name mismatch’ functionalities have been merged into a single ‘Accept mismatch’ function.

FPGA Control pin verification:

• enabled: use name matching.
• disabled: they need to be manually accepted.

FPGA ground pin verification:

• strict: PCB signal must a ground net.
• lenient: PCB can also match by name or by ground net.
• disabled: No checking, requires user accepted mismatch to be set.

FPGA power pin verification:

• strict: Voltage on both side must be present and match.
• lenient: If no voltage is present on both sides, use name matching.
• disabled: No checking, requires user accepted mismatch to be set.

The above options can be set (independently) in the Pin view matching and project verify options, and verify wizard dialog.

The use PCB derived netname checkbox in column 5 of the matching rules has been replaced with a selection box ‘PCB source’ with 4 choices:

• Name: name of the net connected to the FPGA pin.
• Derived: the name found on the opposite side of a resistor or capacitor.
• Any: either Name or Derived.
• Dangling: requires a net to be a dangling wire.

The ‘Clear unused PCB net types‘ is only enabled when it can be set and is used to removed voltage and ground settings on nets which are no longer present in the netlist.

PCB netlist formats

Fabrication netlist format IPC-D-356 (often present with the Gerber data) has been added. The netlist type of a net (power, ground, normal) can be set on any net. In the past power (with a voltage value) could only be set on a net connected to a FPGA power pin.

If a PCB net is manually marked as being a ground net we will now show this in the pin view by adding ' (-> GND)' to the name.

HTML generator

Added the bank number to the tables ‘Pin list by severity’ and ‘List by FPGA pin’. Replaced fixed font sizes by ‘em’ and improved header. Replaced named anchors by ‘id’ attributes.

Wiring a Cadence Allegro symbol based on a CSV file

The dialog to wire non-FPGA symbols in Cadence Allegro (Tcl command Ioc::SchematicCsvDlg) has been extended with a ‘Column for the port’ entry. It allows you to use a specific port for a signal. When it is set the ‘Ports options’ entry is ignored. The ports used need to be present in the Allegro SKILL configuration file.

Enhancements

• Added entry 'Change accept comment' to the Pin view context menu to change comment on a user accepted mismatch.
• Show total number of rule matches in the rules dialog.
• Allegro pin group editor: added sort-able header, inverted discard question and directly load file after selecting it.
• Show LVDS partner of a pin in the tooltip.
• Added filter item (Pin view and Device view) to hide all pins which are equal on current and alternate device.
• Improved automatic detection of RINF netlist files (when extension is not.frs or .frp).

Problem fixes

• Id 2202: option to save data source locations relative to project path.
• Id 2187: user option to disable beep when error message is sent to console.
• Id 2177: windows monitor screen coordinates can be negative, causing various widget position errors.

FPGA device support

The following device families (or additional devices) have been added:

• Efinix:
  The FPGA vendor Efinix has been added to the supported FPGA vendors with the families Trion and Titanium.
  This release does not support reading or writing the Efinix constraints file.
• Intel: Device updates Agilex, Arria 10, Cyclone 5 / 10 / 10LP, MAX 10, Stratix 5 / 10
• Lattice:
  Certus-NX, CertusPro-NX, ECP5, MachXO3, MachXO5-NX
  The Lattice pinlist parser now also extracts DriveStrength/PullMode/SlewRate properties.
• Microsemi:
  Igloo2, SmartFusion2, PolarFire, PolarfireSoc.
  The Microsemi report files ‘..._bankrpt.rpt’ and ‘..._netlist_resources.rpt’ are processed to extract bank voltage information and core/pll voltage values.
  
• Xilinx:
  Akintex7, Artixup, VersalAICore, VersalPrime, VersalPremium, QrKintexu, QversalAiCore, Zynqup, QZynqup and ZynqupRFSoc.

Download IO Checker 5.0 now:

• Software (including manual)