HDL Works
| SPR | Title | Released | Description |
|---|---|---|---|
| 2093 | Generic name shadowing an constant (Lint DR3) is not reported | 3.0.2 | Generics and constants defined in the entity declarative region seem not to be used in the Lint DR3 check. |
| 2084 | No VHDL object name check for enumeration literals | 3.0.2 | There is no way to check the naming convention for enumeration literals. |
| 2083 | VHDL object name check does not check process name if process has no label | 3.0.2 | If a process has no label no error is issued even if the regular expression indicates the process should have a name. |
| 2080 | Verilog lint check SS6 doesn't trigger | 3.0.2 | Multiple assignments in different always statement don't trigger a SS6 check. |
| 2069 | Unused VHDL 2008 generics type/function items fail CP14 check | 3.0.2 | VHDL 2008 allows generics of type type/function. Unused items of these types are not reported and are not checked for adherence to coding standards. |
| 2062 | Crash in SystemVerilog parser after syntax error | 3.0.1 | As title |
| 2057 | VHDL linter CP14 false positive | 3.0.1 | When a component instantiation contains a function in the formal part of a port association this is not recognized. |
| 2050 | VHDL Lint check on range for an integer type | 3.0.1 | Add a lint check that signal or variable using an integer/natural/positive has a range constraint. |
| 2036 | Fuzzy parser does not detect end of package correctly | 3.0.1 | If a package contains a package instantiation statement it is possible the end of the package is treated as the end of the package instantiation. |
| 2030 | Incorrect VHDL-1101 error message | 3.0.1 | |
| 2025 | Modelsim error reporting changed | 3.0.1 | Some Modelsim errors have a changed format (string '(suppressible)' after the string '** Error') failing the error recognition. |
| 2022 | VHDL linter does not report all Misc12 (signal has neither asynchrous reset nor initial value) cases | 3.0.1 | Conditional signal assignments are not handled correctly. |
| 2019 | VHDL linter CP 14 false positive | 3.0.1 | False positive inside a procedure in a package. |
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