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Fixed Problems in HDL Companion 3.2 Rev 2
June 20, 2023

2270 (System)Verilog linter SS14/Misc12 false positives 3.2.2 Verilog signals which behave like VHDL variables (and don't infer a register) should not issue SS14/Misc12 messages.
2263 Lint message CP7 not tiggered for numeric_std signals 3.2.2 VHDL linter now also issues lint messages when comparing different ranges for types defined in numeric_std.
2247 Incorrect command line behaviour of the batch version 3.2.2 The batch version of HDL Companion always expects a project file, either explicit or as argument 1 passed to the TCL script.
2242 Topological sort fails in mixed verilog / VHDL design 3.2.2 The hierarchical view only shows one level.
2240 Error VERI-1128 does not lead to error icon in the file/object view 3.2.2 As title
2239 Xilinx XPR project file import fails on use of PPRDIR variable 3.2.2 Variable was not set for XPR file version 7 import
2227 Fuzzy parser crash on back tick 3.2.2 Parser crashes on use of back tick like:
  report "Error: value out of range " & signal`value
2226 False positive latch detected (Misc2) message on variable 3.2.2 A WHEN / ELSE construct on a variable leads to a incorrect Misc2, latch detected message.
  Lint message CP7 not always tiggered 3.2.2 The issue with the disappearing lint message occurred after a partial analyze.
  Improved support for high resolution monitors 3.2.2 Improved icon scaling.
Added font size increment setting to user preferences
2187 User option to disable annoying beep when errors are sent to the console window 3.2.1 As title
2179 VHDL Misc 8 lint 3.2.1 Check now also reports use of positional generic map (if there are multiple generics).
2177 Scriptum completion dialog appears on the wrong monitor 3.2.1 In a dual monitor configuration with the right hand monitor being primary and Scriptum on the left hand monitor, the small dialogue box for word completion pops up on the left hand edge of the right hand monitor.
2163 Lint check SS5 never hits 3.2.1 Lint check SS5 (avoid multiple waveforms) is never hit in VHDL for a VhdlConditionalSignalAssignment.
1678 Coding standards on files 3.2.1 Add a check on the maximum line length
VHDL Linter 3.2.1 Improved VHDL lint and reporting:
CP7: check function/procedure arguments
CP7: check function return value
Misc6: improved reporting
Verilog Linter 3.2.1 Improved checking for CP11/CP12/Misc8/Misc9

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