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Fixed Problems in HDL Companion 3.3 Rev 1
November 21, 2023

2290 SystemVerilog CP7 linter false positive 3.3.1 SystemVerilog built-in functions of queues where ignored.
2279 New lint checks 3.3.1 Implemented basic DO254 Safe Synthesis checks for SS8/SS9/SS10 (both in Verilog and VHDL):
  SS8: Avoid Clock Used as Data
  SS9: Avoid Shared Clock and Reset Signal
  SS10: Avoid gated clocks
2275 Incorrect (System)Verilog dependencies 3.3.1 When a selected name refers to an instance, but a module/interface with the same (primary) name is present an incorrect dependency to this module/interface is added.
2207 Retain selection in the browsers 3.3.1 After analyzing files the selection in the browser widgets is lost.

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