HDL Works
SPR | Title | Released | Description |
---|---|---|---|
Mentor keyin netlist | 2.0.3 | Support for Mentor Graphics keyin netlist format. | |
ISCF netlist | 2.0.3 | Support for Intel Schematic Compatibility Format (ISCF) netlist format. | |
ODB++ | 2.0.2 | Preliminary support for ODB++ (directory structure only). | |
Altium Designer extension | 2.0.2 | Added support for our own Altium Designer extension and place pin labels in the XML netlist extraction. | |
2061 | PCB properties dialog doesn't show value of the 'Voltage extraction' property | 2.0.2 | The Allegro option checkbox 'Voltage extraction: Ignore values' is always unchecked. |
2059 | Part properties are never updated | 2.0.2 | Part properties are not updated after reparsing a PCB file. |
2046 | Pins are compared in a case-sensitive manner | 2.0.1 | The matcher sees pins like 'A1' and 'a1' as different pins. Connectors using alpha-numeric pin names which differ only in case are not matched. |
2021 | Non-existent reference designator can be specified for an FPGA | 2.0.1 | Reference designators are now presented in a dropdown list and should be present in the netlist. |
CSV PCB import | 2.0.1 | Possibility to import a pcb description using a generic CSV file. |
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