EASE 9.2: Problem fixes and improvements

SPR	Title	Released	Description
2150	Crash when loading corrupt design	9.2.7	Deleting generate ports in a specific order resulted in a in-consistent project which can crash the application.
2149	Crash in Verilog linter	9.2.7	Empty string parameters used in mathematics could lead to a crash.
	Diagram port line color	9.2.6	Changing the default fill color for a port had no effect on diagram ports: the line color was used as fill color.
	Mixed language support	9.2.6	Fixed issues when entities and modules with the same name were present in different libraries.
2130	SystemVerilog Misc6 linter false positives	9.2.6	If a SystemVerilog instance uses the ".*" wildcard for ports this is not handled correctly by the linter resulting in Misc6 messages.
2113	VHDL fuzzy parser always ignores synthesis pragmas	9.2.6	The fuzzy VHDL parser always ignores synthesis pragmas (even when told to follow them). This can cause problems in the real VHDL parser as not all dependencies may have been detected by the fuzzy parser.
2108	Data files not recognized in a directory containing extended characters	9.2.6	Files stored below a folder containing extended characters (like é or è) are not found inside an EASE project.
2104	Text string pasted from property tables contains duplicate quotes	9.2.5	All double quotes in text copied from property tables and pasted in other documents are duplicated.
2103	Multiline textedit can not be activated for actual/default values	9.2.5	The generic/port property pages don't allow to edit default/actual values in multiline mode.
2102	VHDL architecture to block diagram conversion fails	9.2.5	The 'Create block diagram architecture' function fails when the entity uses package numeric_std in VHDL 2008 mode and has not yet been saved.
2101	When using VHDL direct instantiations not all the architectures are always generated	9.2.5	When using direct instantiations inside an internal configuration and there are instances referring to different architectures of the same entity only the default architecture will be generated during hierarchical generation.
2100	When double clicking on a component that uses a direct instantiation the specified architecture should be opened	9.2.5	As title
2095	VHDL architectures not generated in correct order	9.2.4	If no explicit binding is specified for an instantiation VHDL specifies that the last analysed architecture will be used. This means we have to generate the default architecture as last architecture (at least when multiple architectures are generated in a single file).
2094	Bindings for nested VHDL configurations are lost during load	9.2.4	When inside a VHDL configuration an instantiation is bound to another configuration the data is saved correctly but after loading the project again the bindings for the nested configuration are no longer correct.
2092	Generic name shadowing an constant (Lint DR3) is not reported	9.2.4	Generics and constants defined in the entity declarative region seem not to be used in the Lint DR3 check.
2090	Doxygen tags cannot be added using the comment fields	9.2.4	An additional space is always placed between the '--'or '//'' and the comment text. So a Doxygen marker --! can never be added.
2089	Notes are not shown in the generated HTML documentation	9.2.4	Notes are just ignored in the HTML documentation.
2080	Lint check SS6 not triggered.	9.2.3	Improved Verilog linting check for multiple drivers (SS6) in inital and always statements.
	Possible crash when deleting a package	9.2.3	Deleting a package while there were still package uses for this package at the architecture level could cause a crash.
	Verilog include files	9.2.3	EASE verification and Fuzzy parser did not use correct directory for Verilog include files.
2078	Project incorrect after importing HDL for existing entity in "Interface only" mode	9.2.2	When using HDL import for an existing entity in mode 'Interface only' all diagram ports for other entities will be disconnected and move to the left top of the sheet.
2077	VHDL type name reference should keep original case instead of using case of definition	9.2.2	VHDL-2008 package std_logic_1164 contains: subtype STD_LOGIC is resolved STD_ULOGIC; VHDL-93 package std_logic_1164 contains: SUBTYPE std_logic IS resolved std_ulogic; During VHDL import references are resolved and the name of the subtype declaration is used instead of the name of the reference. EASE should keep the name of the reference even if it does not match (uppercase/lowercase) of the declaration.
2076	Synchronous transition priority ignored	9.2.2	When the async reset transition is changed into a synchronous transition its priority is ignored and always set to the last global prority.
2032	Remove trailing whitespace in editor tables when pasting text	9.2.1	Automatically remove trailing whitespace in table entries of the port/generic list of the entity property dialog when pasting data.
2026	Easy way to connect selected ports using CBN tags	9.2.1	There should be an easy way to connect a number of ports using CBN tags (even if these ports do not have the same name).
1928	Use of generic default value in VHDL component declaration / instantiation can cause problems	9.2.1	Added VHDL lint check to check if generic default value in component declaration matches generic default value in entity declaration.
1837	Improve loading performance of linked libraries	9.2.1	Added caching of database file content so database files inside linked libraries will only be loaded from (network) disk once.
1801	Easier way to edit name property of a port/generic/tag in a diagram	9.2.1	Use double click on the object to edit its properties.
1391	Allow 'toggle mode' for all elements of a virtual record	9.2.1	When a port has a virtual record type that contains a lot of elements and you want to toggle the direction for all elements in the entity properties dialog it would be nice if you could do this by selecting the virtual port instead of having to select all individual elements.

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Problems fixed in EASE 9.2 Rev 7