Problems fixed in EASE 9.2 Rev 2

SPRTitleReleasedDescription
2078 Project incorrect after importing HDL for existing entity in "Interface only" mode 9.2.2 When using HDL import for an existing entity in mode 'Interface only' all diagram ports for other entities will be disconnected and move to the left top of the sheet.
2077 VHDL type name reference should keep original case instead of using case of definition 9.2.2 During VHDL import references are resolved and the name of the subtype declaration is used instead of the name of the reference. We should keep the name of the reference even if it does not match (uppercase/lowercase) of the declaration.
2076 Synchronous transition priority ignored 9.2.2 When the async reset transition is changed into a synchronous transition its priority is ignored and always set to the last global prority.
2032 Remove trailing whitespace in editor tables when pasting text 9.2.1 Automatically remove trailing whitespace in table entries of the port/generic list of the entity property dialog when pasting data.
2026 Easy way to connect selected ports using CBN tags 9.2.1 There should be an easy way to connect a number of ports using CBN tags (even if these ports do not have the same name).
1928 Use of generic default value in VHDL component declaration / instantiation can cause problems 9.2.1 Added VHDL lint check to check if generic default value in component declaration matches generic default value in entity declaration.
1837 Improve loading performance of linked libraries 9.2.1 Added caching of database file content so database files inside linked libraries will only be loaded from (network) disk once.
1801 Easier way to edit name property of a port/generic/tag in a diagram 9.2.1 Use double click on the object to edit its properties.
1391 Allow 'toggle mode' for all elements of a virtual record 9.2.1 When a port has a virtual record type that contains a lot of elements and you want to toggle the direction for all elements in the entity properties dialog it would be nice if you could do this by selecting the virtual port instead of having to select all individual elements.
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