Problems fixed in EASE 9.3 Rev 1

2140 When changing signal type from vector to non-vector the range should be cleared 9.3.1 When the VHDL signal type changes from vector to non-vector we now store the old range information and clear and disable the entry in the user interface. When the type changes to a vector type the old range information is restored and the range gadget is enabled again.
2131 New lint check: report assertion statements that do not have a report clause 9.3.1 Check is disabled by default.
2130 SystemVerilog Misc6 linter false positives 9.3.1 If a SystemVerilog instance uses the ".*" wildcard for ports this is not handled correctly by the linter resulting in Misc6 message.
2116 Allow to add multiple external files in one action 9.3.1 It is now possible to add/delete/edit multiple external documents as long as they belong to the same parent (project/library/entity/...)
2115 Open external file with regular text editor 9.3.1 An external document added to EASE cannot be opened/edited when the file extension is not registered.
2111 EASE fails to save/restore user settings on Windows 9.3.1 The save/restore of user settings doesn't work on Windows when the username contains extended characters.
2110 Support for the Kate editor on Linux 9.3.1 It is now possible to specify a session id when using an external editor (using %s to denote the session identifier). The name of the workspace directory (without extension) will be used as session identifier.
2108 Files not recognized in a directory containing extended characters 9.3.1 Files stored below a folder containing extended characters (like or ) are not found by EASE.
2106 Extend diagram 'Push down' function 9.3.1 Extend the push down function to a VHDL block or generate statement.
2098 TruthTable editor doesn't restore current cell on undo/redo 9.3.1 Active item and selection are now restored
2097 Synchronous reset of an FSM needs improvement 9.3.1 The generated HDL code of EASE, when using multiple global transitions, is an if/else if/else which is not recognized by the synthesis tool. It should be an if / else, with the other global transitions inside the else part.
2096 Improved support for instantiations in VHDL 9.3.1 Added ability to have a configuration specification for the entity/architecture/configuration to use for an instance.
2005 Support for attribute specifications on HDL signal declarations 9.3.1 In the HDL Declarations dialog you can specify attributes on signals.
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