HDL Works

HDL Works

Problems fixed in EASE 9.3 Rev 7
January 10, 2023

2227 Fuzzy parser crash on back tick 9.3.7 Incorrect use of the back tick operator crashed the fuzzy parser
2223 No standard packages present in VHDL 2002 mode 9.3.7 The 'Standard packages' dialog is empty when the VHDL mode is set to 2002.
2220 After resizing diagram to fit content zoom actions may behave strange 9.3.7 Happened when obect was placed outside the sheet boundary.
2219 In some cases undo is not possible in the FSM editor 9.3.7 After translating a line segment of an FSM transition the undo was not enabled.
2218 Deleting a used architecture can cause a crash 9.3.7 As title
2217 FSM line segments can get off-grid 9.3.7 Certain state moves result in FSM line segments to be off grid.
2208 When component is selected in database view and another component is moved using keyboard the selection changes 9.3.7 When the browser is rebuilt the highlights will be restored and the objects referred will be selected again in the diagram editor.
2205 Empty declarations object is not deleted 9.3.6 When deleting all entries from a declarations object it will not be deleted.
2203 Incorrect use clause 9.3.6 Use clauses are generated while property on entity "Do not generate use clauses ..." is set.
2200 Infinite loop in net tool 9.3.5 Infinite loop toolwhen creating diagram port using net tool starting at (virtual) port without a name.
2186 Text file not removed after Subversion un-checkout 9.3.5 In some cases text files are not deleted from disk when an un-checkout is performed. Issue occurred when an un-checkout of a text file containing stimulus data was performed while it was still open (and locked) by Modelsim.
2181 VHDL import fails when referring to library work 9.3.4 Import fails for a package which is already present in EASE in a named library
2178 Using copy and paste in entity property dialog to copy generics gives weird results 9.3.4 Depending on the selected columns the paste does not behave as expected.
Corporate environment variables could not be set 9.3.4 Only existing variables could be changed.
2176 VHDL component specifications for components with a simple if/for generate generated in the wrong scope 9.3.3 When using VHDL instantiation style 'Component declarations and configuration specifications' for instances with a simple if/for generate, the configuration specification is generated at architecture level instead of inside the generate block.
2172 Comment of bit code of a one-hot encoded state is incorrect. 9.3.3 The bit code of a one-hot state machine (shown in comment with the states and generated code) is in reverse bit order.
2171 Incorrect VHDL CP8 message 9.3.3 Impure functions or procedures defined in an architecture and reading signals from the entity/architecture and invoked inside a combinatorical process, require that those signals are on the sensitivity list.
2170 Incorrect VHDL CP14 lint message 9.3.3 When using overloaded functions function usage is not detected correctly.
2169 Incorrect VHDL SS14 lint message 9.3.3 Conditional variable assignment statements like
  MyVar := '0' when (x = y)
are not handled correctly and may result in an SS14 message about x.
2163 Lint check SS5 never hits 9.3.3 Lint check SS5 (avoid multiple waveforms) is never activated in VHDL. The 'after' keyword was used to determine if the code was behavioral, which disables the check.
Vivado simulator 9.3.3 Recent Vivado simulator versions did not start properly on Windows 10.
2167 Toplevel marker not correctly imported from older projects 9.3.2 The top-level marker is not correctly imported in EASE 9.x for projects saved with older EASE versions. The top-level marker is shown in the browser, but updated and reset when generating code for the marker.
2166 External user package is not generated 9.3.2 Old style user packages which use an external file could be added to the generated VDHL code. The code generation no longer works.
2165 Doxystyle comment does not work for included text of type Comment 9.3.2 Some comment fields still added a space after the --
2164 Regular diagram comment for an FSM not generated 9.3.2 For an architecture which has a state machine the regular diagram comment is not generated.
2159 Verilog import fails on instances present as modules in EASE 9.3.2 EASE doesnot find the modules already present in its own libraries.
2140 When changing signal type from vector to non-vector the range should be cleared 9.3.1 When the VHDL signal type changes from vector to non-vector we now store the old range information and clear and disable the entry in the user interface. When the type changes to a vector type the old range information is restored and the range gadget is enabled again.
2131 New lint check: report assertion statements that do not have a report clause 9.3.1 Check is disabled by default.
2130 SystemVerilog Misc6 linter false positives 9.3.1 If a SystemVerilog instance uses the ".*" wildcard for ports this is not handled correctly by the linter resulting in Misc6 message.
2116 Allow to add multiple external files in one action 9.3.1 It is now possible to add/delete/edit multiple external documents as long as they belong to the same parent (project/library/entity/...)
2115 Open external file with regular text editor 9.3.1 An external document added to EASE cannot be opened/edited when the file extension is not registered.
2111 EASE fails to save/restore user settings on Windows 9.3.1 The save/restore of user settings doesn't work on Windows when the username contains extended characters.
2110 Support for the Kate editor on Linux 9.3.1 It is now possible to specify a session id when using an external editor (using %s to denote the session identifier). The name of the workspace directory (without extension) will be used as session identifier.
2108 Files not recognized in a directory containing extended characters 9.3.1 Files stored below a folder containing extended characters (like é or è) are not found by EASE.
2106 Extend diagram 'Push down' function 9.3.1 Extend the push down function to a VHDL block or generate statement.
2098 TruthTable editor doesn't restore current cell on undo/redo 9.3.1 Active item and selection are now restored
2097 Synchronous reset of an FSM needs improvement 9.3.1 The generated HDL code of EASE, when using multiple global transitions, is an if/else if/else which is not recognized by the synthesis tool. It should be an if / else, with the other global transitions inside the else part.
2096 Improved support for instantiations in VHDL 9.3.1 Added ability to have a configuration specification for the entity/architecture/configuration to use for an instance.
2028 Issue warning when trying to perform uncheckout on newly created entity 9.3.1 When an uncheckout action is (accidentally) performed on a newly created entity this will result in an empty entity.
2005 Support for attribute specifications on HDL signal declarations 9.3.1 In the HDL Declarations dialog you can specify attributes on signals.
Home Company Products
Sales Support Site Map
Home Company Products Sales Support HDL Corner Site Map
Home dot Company dot Products dot Sales dot Support dot HDL Corner dot Site Map

Copyright © 2004 - 2024 HDL Works