HDL Works

HDL Works

Problems fixed in EASE 9.4 Rev 5
March 19, 2024

2310 Unmodified checked-in user package regenerated when using update HDL from marker 9.4.5 An unmodified checked-in user package (located in a managed library that uses a tag) is regenerated when updating HDL from marker.
2290 SystemVerilog CP7 linter false positive 9.4.5 SystemVerilog built-in functions of queues where ignored.
2288 Synthesis pragmas (partially) ignored during VHDL import 9.4.4 During VHDL import the use of pragma statements at the end of a process can cause incorrect import.
2275 Incorrect (System)Verilog dependencies 9.4.4 When a selected name refers to an instance, but a module/interface with the same (primary) name is present an incorrect dependency to this module/interface is added.
2270 (System)Verilog linter SS14/Misc12 false positives 9.4.3 Verilog signals which behave like VHDL variables (and don't infer a register) should not issue SS14/Misc12 messages.
2268 Unable to move single (straight) transition 9.4.3 When selecting 2 straight transitions (using area selection) between 2 states you can move them. When selection only 1 straight transition between 2 states you cannot move it.
2263 Lint message CP7 not tiggered for numeric_std signals 9.4.3 VHDL linter now also issues lint messages when comparing different ranges for types defined in numeric_std.
2242 Topological sort fails in mixed verilog / VHDL design 9.4.3 In mixed language designs the files were not always presented to the external tools (simulator) in the correct order.
2232 Variable in FSM undefined 9.4.3 A variable defined with HDL declarations dialog in an FSM and only used in the default action on states, is not defined in the HDL when there no actions on states present.
2230 Incorrect connection properties after VHDL import 9.4.3 A VHDL component with std_logic/std_logic_vector ports connected to complex type of an array of records has incorrect connections properties.
  Toolflow 9.4.3 Added 2 buttons for the Efinix synthesis tool Efinity.
2229 Concurrent statement blocks placed on top of each other 9.4.2 In some cases numerous concurrent statements blocks are placed on top of each other after VHDL import.
2227 Fuzzy parser crash on back tick 9.4.2 Incorrect use of the back tick operator crashed the parser
2226 False positive latch detected (Misc2) message on variable 9.4.2 A WHEN / ELSE construct on a variable leads to a incorrect Misc2: latch detected message.
2225 Multiline comment for port/generic causes problems 9.4.2 It is possible to paste multiline comment in the entity properties dialog for ports and generics.
2223 No standard packages present in VHDL 2002 mode 9.4.2 The 'Standard packages' dialog is empty when the VHDL mode is set to 2002.
2222 Wrong label selected in the FSM action properties dialog 9.4.2 Last label in the FSM action properties gets selected when adding a new label, instead of the new added label.
2220 After resizing diagram to fit content zoom actions may behave strange 9.4.2 Happened when obect was placed outside the sheet boundary.
2219 In some cases undo is not possible in the FSM editor 9.4.2 After translating a line segment of an FSM transition the undo was not enabled.
2218 Deleting a used architecture can cause a crash 9.4.2 As title
2217 FSM line segments can get off-grid 9.4.2 Certain state moves result in FSM line segments to be off grid.
2216 Use selected label name when creating a new one 9.4.2 When creating a new FSM action/condition label using the "New" button in the action/condition properties dialog present the current one as default.
2208 When component is selected in database view and another component is moved using keyboard the selection changes 9.4.2 When the browser is rebuilt the highlights will be restored and the objects referred will be selected again in the diagram editor.
2212 In FSM actions dialog order the actions alphabetically 9.4.1 As title
2208 Incorrect component selection after move 9.4.1 When component is selected in database view and another component is moved using keyboard the selection changes.
2206 Other icons for the Siemens Questasim simulator 9.4.1 Have different icons to distinguish them from the Modelsim icons.
2197 Add 'Underflow protection' to the FSM state wait cycle timer HDL code. 9.4.1 When using wait cycles in an FSM state which are defined using generics or constant the cycle delay may become negative. This will result in either a simulation or synthesis failure.
2195 Copying process ports 9.4.1 When copying a process port the existing HDL code for the process should not be changed.
2194 Add task button in editor to view generated HDL output 9.4.1 As title
2187 Disable beep in the console window 9.4.1 User option to disable annoying beep when errors are sent to the console window
2183 More shortcuts in the diagram editor 9.4.1 t,l: toggle label visibility for selected objects
t,m: to toggle port mode for selected ports
m,d: to move selected labels to their default location.
2179 Lint check for generics in the component map 9.4.1 A new lint check to verify that generics in the component generic map are
1. Assigned by name (in stead of by position)
2. Are all listed in the generic map
2175 Support for type generics in entities 9.4.1 In VHDL 2008 mode generics on an entity can be of type constant/function/procedure/type.
2168 Improved (HTML) documentation generation 9.4.1 Added tables for generics and ports.
2143 Easier way to use similar layout for related symbols 9.4.1 For repeated HDL imports, have a way to copy an entity symbol layout
2141 Regular expression based name change on ports/signals 9.4.1 In some cases imported code contains lots of ports/signals that have a common prefix (e.g. ddr4ef_mem_mem_). It would be nice if it was possible to change these names using regular expressions.
Local signals incorrectly placed on the FSM sensitivity list 9.4.1 Signals declared in the FSM declaration dialog and used in the actions of the asynchronous reset transition are placed on the sensitivity list independent from beeing at the left hand or right hand side of an expression.
2037 Combination of selected name and actual in port connection dialog 9.4.1 When using both selected and actual name in the port connection dialog the shown label is incorrect.
2006 Visualize if nets have attribute specifications 9.4.1 Add some kind of graphical indication for nets that have one or more attributes specifications.
Home Company Products
Sales Support Site Map
Home Company Products Sales Support HDL Corner Site Map
Home dot Company dot Products dot Sales dot Support dot HDL Corner dot Site Map

Copyright © 2004 - 2024 HDL Works