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Problems fixed in EASE 9.5 Rev 2
March 19, 2024

SPRTitleReleasedDescription
2310 Unmodified checked-in user package regenerated when using update HDL from marker 9.5.2 An unmodified checked-in user package (located in a managed library that uses a tag) is regenerated when updating HDL from marker.
2308 Incorrect fuzzy message on constant function argument 9.5.2 Constant arguments with an explicit type argument (ieee.numeric_std.signed) of a function definition within an architecture cause a fuzzy message.
2304 Alias statements seen as component declarations 9.5.2 Some alias statements on variables or signals are treated (and shown in the detailed view) as component instantiations.
2294 Incorrect fuzzy messages about package not being found 9.5.1 Packages referred to as 'work.pkg..' were reported not found.
2292 Hot error navigation to an FSM label does not open the FSM diagram 9.5.1 When using hot error navigation for a message relating to an FSM label (e.g. label never used) the FSM label dialog is opened, but the FSM diagram is not. The FSM diagram should also be opened in the editor.
2290 SystemVerilog CP7 linter false positive 9.5.1 Problem is with builtin functions: they have no formal arguments so we do not know if the arguments are read or written.
2288 Synthesis pragmas (partially) ignored during VHDL import 9.5.1 During VHDL import we try to extract blocks of code (e.g. content of process/architecture). In some cases we do this using the position of the last token in the block we wanted to extract. This does not work if the block ends with a pragma statement as this is not a token.
2279 New lint checks 9.5.1 A number of DO254 Safe Synthesis checks:
SS8: Avoid Clock Used as Data
SS9: Avoid Shared Clock and Reset Signal
SS10: Avoid gated clocks
These checks are only performed local to the architecture.
2269 HDL Import: support for unary operators in port map 9.5.1 Add unary operators to the port connection property in the block diagram, instead of creating a text architecture file.
2265 Support for VHDL import from command line 9.5.1 Add possibility to create EASE projects from text files on the command line.
2255 Control HDL generation order of concurrent statements in a block diagram 9.5.1 It is now possible to manually specify an order for the blocks. This order will also be used by the HDL generated.
2254 Simply subdesign import/update 9.5.1 Have a better way of importing an EASE entity and its layout without its hierarchy (to be used as black box) into another EASE project. .
2250 Add a message dialog when opening a project created with an older version 9.5.1 To prevent changing/saving a modified project to a newer database format add a message dialog when opening a project using an older database format.
2248 Remove temporary files function leaves empty directories 9.5.1 Please remove them as well.
2241 Add option to disable 'Net has only one connection' verification warning 9.5.1 Single connection wires are often present at testbenches or local signal at processes. Add a way to suppress these messages.
2221 Ability to specify Verilog attributes on wires and ports 9.5.1 Attributes like:
(* direct_enable = "yes" *) input ena3;
2210 Add keyboard shortcut (M, D) in FSM editor 9.5.1 Move label to default position.
2107 Extend graphical generate statement 9.5.1 VHDL 2008 supports if-elseif-else and case generate statements.
316 Ordering components in a diagram 9.5.1 It is now possible to manually specify an order for the blocks. This order will also be used by the HDL generated.
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