IO Checker 4.0: Problem fixes

SPR	Title	Released	Description
2049	Allegro pin group editor keeps reporting changes	4.0.2	Once changes have been made to a PIN_GROUPS the dialog continues to report that changes are present when you close the dialog.
2035	User/corporate rules dialog does not save flag	4.0.2	The 'Use PCB derived name' flag is ignored.
2033	IO Checker will crash when specifying a rule with an empty name	4.0.2	The ruls dialog allows to save a rule without a name, when it is not active. However it will crash in the apply.
2024	Re-wiring symbol in Allegro after pin swap can result in duplicate wire names.	4.0.2	The wiring program doesn't remove wires for which no data is specified in data table. So the unconnected pin gets a new wire (with correct name) but the old (which should be unconnected) is not removed.
	Altera device update	4.0.2	Device updates for Cyclone 10 and Stratix 10
	Microsemi device update	4.0.2	Device updates for Polarfire and RTG4
	Xilinx device update	4.0.2	Device updates for QVirtexup, Zynqup, VirtexupHBM, Virtexup58G
2014	Verilog generated from PCB data contains wires declarations	4.0.1	Removed wires and generate ANSI style Verilog module
2012	MACHXO pins marked as dedicated control pins	4.0.1	MACHXO2 and MACHXO3 pins DONE, PROGRAMN and INNIT are set to be dedicated control (and not to be used in the constraints) while beeing dual use.
1977	Verify that the regular expression in rules dialog is valid	4.0.1	When you specify a regular expression like 'user_(\d+' there is no feedback that the expression is invalid. (Only that the match count will be 0)
1965	Wire both $LOCATION and LOCATION components	4.0.1	In some sheets in Cadence Allegro the FPGA components uses both LOCATION and $LOCATION reference designator. The wiring routine should support in the same sheet.
1942	Improve HDL/Constraint generation for Altium Designer LVDS signals	4.0.1	In Altium Designer it is required that all LVDS signal pairs end with _n and _p. This is also the case for array signals. So an LVDS array of signals in Altium Designer looks like: sig<4>_p, sig<3>_p, ... (and n side, a<4>_n , a<3>_n).
1923	Improve caption of verification window	4.0.1	IO Checker should adjust the caption when only doing a file status verification (vs a project verification).
1876	Add a check to verfiy all HDL signals have a location constraint	4.0.1	It is now only possible to see in the HDL Signal view if all signals have a pin location constraint. (Using the view filter).
1577	Improved generation of both HDL and constraint file from PCB data	4.0.1	HDL and constraint generation is now based on the Signal View. Here you can modify signal names, ranges and direction before generating HDL.

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Problems fixed in IO Checker 4.0 Rev 2