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Problems fixed in IO Checker 4.1 Rev 2

2108 Data files not recognized in a directory containing extended characters 4.1.2 Files stored below a folder containing extended characters (like é or è) are not found inside IO Checker.
Vectored signals could loose pin assignment when editing properties 4.1.2 Vectored signals created from PCB import would loose pin assignment after a name change in the signal properties.
Improved support for retrieving properties using Tcl interface. 4.1.2 Most data commands have a propnames option to retrieve property names.
Intel device update 4.1.2 Device updates for Agilex, Stratix 10
Lattice Semiconductor device update 4.1.2 Device updates for ECP5
Microsemi device update 4.1.2 Device updates for Igloo2, SmartFusion2, Polarfire
Xilinx device update 4.1.2 Device updates for QVirtexup, Versal AI Core, Virtexup, VirtexupHBM, Virtexup58G, ZynqupRFSOC
2085 Net set unconnected by unconnected net pattern still used in verification 4.1.1 PCB net names which match the NC netname property are still used in the verification.
2070 Direction info is not extracted from Microsemi pin report file 4.1.1 Added extraction for column Direction, when present.
2065 IO Standard not removed 4.1.1 When using the 'Fix location constraints' dialog the suggested IO standard removal, for a pin, for which the signal will removed, is not performed. The IO standard remains present in the Pin view.
2064 Unable to start Schematic update when no pin/constraints file is present 4.1.1 The Schematic update dialog doesn't start when there is no pin/constraint file and constraints have been created using CSV import or by hand.
2063 VHDL package files cannot be removed 4.1.1 Once defined they can never be removed
2060 Add XML netlister to Altium Designer extension 4.1.1 Seperate netlister makes using the netlist on another computer easier.
2058 Reprocessing constraint file should not leave no longer present signals in the view 4.1.1 When all data in the Signal view comes from constraint file(s) and no changes are present reprocessing the (changed) constraint file(s) should not lead signals which appear to be new.
2056 Have more tooltips in the rules dialog 4.1.1 Added tooltips for expressions not containing dollar expressions.
2055 Rules dialog matching tooltip is incomplete 4.1.1 Show actual FPGA signal name in tooltip
2053 Re-use IO Checker instance started from Altium Designer 4.1.1 Every time we export data to IO Checker an new instance is started. Instead it would be better to trigger a reload of the netlist in the project.
2052 Improve Xilinx IO constraints expansion 4.1.1 In Xilinx IO constraints can be set for an array using the signal name. IO Checker required a wildcard.
2051 Allow sorting of pin/signal view using the header 4.1.1 Clicking on a section in the header should sort that section column.
2035 User/corporate rules dialog does not save flag 4.1.1 The 'Use PCB derived name' flag is ignored.
2016 Extend CSV component wiring for Cadence Allegro 4.1.1 The CSV wiring should be able to wire different components (so multiple reference designators) in a Cadence Allegro.
2013 Option to ignore VOLTAGE data in Cadence board files 4.1.1 When the VOLTAGE property on a net doesn't denote the voltage value of the net it should be ignored to avoid useless values.
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