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Problems fixed in IO Checker 4.2 Rev 3
September 12, 2022

2193 No HDL units extracted from specified HDL file in the project properties dialog 4.2.3 The HDL file, when relative, was preprocessed using the current working directory instead of using the project path.
FPGA Device updates 4.2.3 Updates for Intel Agilex & Microsemi Igloo2 / SmartFusion2
Corporate environment variables 4.2.2 Variables could not be set, only changed
LVDS rename dialog 4.2.2 Changed confusing header labels
FPGA Device updates 4.2.2 Updates for
  Intel Agilex
  Xilinx Artix UltraScale+, Versal AI Core, Versal AI Edge, Versal Prime, Virtex UltraScale+, Zynq(RFSOC) UltraScale+
2153 Use extracted device from the Intel FPGA constraints 4.2.1 When only specifying a constraint file for Intel, the correct recognized device is reported but not used.
2152 Filter option when searching the netlist for reference designators in project properties dialog 4.2.1 On the PCB page of the IO Checker properties dialog we can extract/show all reference designators which exceed a certain pin count. (Default 256). Use some kind of filter to only show designators with the exact number of pins as the selected FPGA.
2151 Browser dialog for CSV export of a view requires existing file 4.2.1 When using the browse dialog in CSV export of the signal/pin view, the browse widget requires an existing file. You cannot specify/select a new file.
2144 Support 2 dimensional arrays in VHDL 4.2.1 As title.
2137 Improve Lattice PAD report parsing for IO standards 4.2.1 The Lattice pad report file adds a postfix (based on signal direction) to the IO Standards reported in the column 'Buffer Type'.
2122 Restore option to create constraints for selected PCB signals 4.2.1 In IO Checker 3.4 you could generate FPGA location constraints for the selected PCB signals in the pin view. This option was removed in 4.0.
2120 Lattice LPF constraint parser does not report duplicate IO standard assignment 4.2.1 No message is given when a signal has 2 different IO standard constraints (the last one is used).
2118 Setting a signal to ground doesn't resolve power error 4.2.1 Ground/power and ground pins should not be matched by name.
2111 IO Checker fails to save/restore user settings on Windows 4.2.1 The save/restore of user settings doesn't work on Windows when the username contains extended characters.
2109 Add Cadence brd file extraction as a separate format 4.2.1 Add a format definition to parse the extraction data generated by the Cadence extracta utility. This allows designers to process the extracted data of a brd file on another computer.
2108 Data files not recognized in a directory containing extended characters 4.2.1 Files stored below a folder containing extended characters (like é or è) are not found.
Improved ISCF parser 4.2.1 Improved error handling and allow parsing of component properties.
FPGA Device updates 4.2.1 Updates for
  Intel Agilex, Stratix 10, Max10, Cyclone10
  Xilinx Versal, Virtex UltraScale+ HBM, Defense-Grade Zynq UltraScale+ RFSoC, Defense-Grade Zynq UltraScale+ MPSoC
  Microsemi Igloo2, SmartFusion2, PolarFire
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