IO Checker 5.2: Problem fixes

SPR	Title	Released	Description
2350	AMD Vivado dictionary support	5.2.1	It is possible to combine Pin and IO Standard assignment in the constraints file in one line using the -dict option: set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18 } [get_ports ETH1_MDC}]
2345	Verify if an IO standard is allowed for a bank/pin	5.2.1	Implemented check per pin for recent Altera (in Quartus(Pro) 23.x) and AMD (Vivado 2024.1) devices
2339	Ability to select derived PCB name when creating constraints	5.2.1	When you have net with has both a name and derived name it would be useful to be able to select which of these 2 names should be used when creating constraints from PCB data.
2285	Device view: have a top and bottom view.	5.2.1	A button is added to switch between the top and bottom view.
	FPGA Device updates	5.2.1	AMD QVersal Premium, Versal (aiedge, hbm, prime, premium) and Zynq. Efinix Titanium & Topaz Altera Renamed Intel back to Altera Agilex 7, Stratix 10 Changed Stratix 3, Stratix 4 and Cyclone 3 families into legacy families. Lattice Semiconductor Avant, MachX05, ECP5, MachXO2 Microchip Renamed Microsemi to Microchip PolarFire, PolarFireSoc

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Problems fixed in IO Checker 5.2 Revision 1To be announced