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EASE: HDL generation and toolflow

The code generator produces HDL output conforming to the IEEE-1076-87/93/2008 VHDL and IEEE-1364-95/2001/2005 Verilog standards. Various options can be set to control filenames, directory structures, which units go where. The code is well formatted and easily readable. The generator is very fast and EASE can directly compile the outputs files for a simulator.

3rd Party Interfacing

EASE has a user configurable third party tool flow interface. A wizard will help the user to select the appropriate tools and set the options for these tools. Extra tool buttons will be added to the GUI for easy access to the selected tools. A list of tools supported by default is provided below. Other tools or vendors are easily added through the Tcl interface.

Simulation tools:

Synthesis tools:

The FPGA Vendor tools from:

Team design and version management Design documentation

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