EASE: HDL generation and toolflow

The code generator produces HDL output conforming to the IEEE-1076-87/93/2008 VHDL and IEEE-1364-95/2001/2005 Verilog standards. Various options can be set to control filenames, directory structures, which units go where. The code is well formatted and easily readable. The generator is very fast and EASE can directly compile the outputs files for a simulator.

3rd Party Interfacing

Simulation tools:

• ModelSim (Mentor Graphics)
• NCSim, Verilog-XL (Cadence)
• ISIM, XSIM (Xilinx)
• Verilogger (SynaptiCAD)
• Riviera (Aldec)

Synthesis tools:

• Altera Quartus
• Synplify (Synplicity)
• Precision
• Xilinx ISE

The FPGA Vendor tools from:

• Altera
• Lattice
• Microsemi
• Xilinx

Team design and version management Design documentation