The state diagram editor supports Moore, Mealy and mixed state machines. Any valid VHDL expression or Verilog statement can be used to define actions and transition conditions. Transitions can be synchronous or asynchronous; outputs can be clocked or combinatorial. The state diagram editor supports a variety of state assignment methods, including binary, gray, one-hot and two-hot. User defined assignment is also supported.
Master – Slave state machines is a concept where a master state machine can start a slave machine and waits until the slave has finished its operation. The slave can be started in any state of the master machine. Ease will generate control signals that synchronize the master and slave machines. Using this functionality users do not have to draw two separate FSM processes and define synchronization signals between the state machines.
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