Generated by
Ease
for
demo
on Thu Jan 13 15:19:29 2022
Back
Index
uart
uart_tb
test
Hierarchy for architecture test of entity uart.uart_tb
Contents
Side Data
Generated HDL
Architecture: test
u1:
clock_gen
:
text
u0:
uart
:
structure
u0:
transmitter
:
structure
u0:
transmit
:
fsm
u1:
receiver
:
structure
u0:
rec_fsm
:
structure
u1:
edgedet
:
rtl
u2:
edgedet
:
rtl
u2:
cntrl
:
rtl
u3:
stim
:
rtl